This logic module takes up to four input signals and outputs the logic function AND, OR, XOR dependent on the input signals. The inputs are normalized so you can use less then the four inputs. It has three NOT functions as well.
The documentation and the Gerber files for download can be found in my website.
This logic module takes up to four input signals and outputs the logic function AND, OR, XOR dependent on the input signals. The inputs are normalized so you can use less then the four inputs.
The documentation and the Gerber files for download can be found in my website.
Nothing special to mention. On page one you see the input and outputs. On page two are the input protection circuitry, the microprocessor and the output buffers. The logic is done in software.
This module takes the incoming gate or trigger and routes it to either of its two outputs. The distribution is software driven, according to a random coin toss. You can select the probability distribution with a potentiometer and an input control voltage. The potentiometer voltage and the control voltage are added together. The probability goes from 0% to 100% at output A and from 100% to 0% on output B.
The documentation and the Gerber files for download can be found in my website.
With this module you can distribute the incoming gate or trigger up to eight outputs. The distribution is software driven. You can select the amount of the used outputs from zero to eight with a potentiometer and an input control voltage. The potentiometer voltage and the control voltage are added together. The mode potentiometer and the mode control voltage selects the algorithm for the distribution. As for the moment (2021 Nov.) only one mode is implemented. Rotating upwards. Any suggestions or programs are welcome.
The documentation and the Gerber files for download can be found in my website.
This module starts as a need for my Shakuhachi 2 Synth project. I was in need for a short Gate Delay of about 10ms (which is easy to realize). But then I thought about a more flexible solution with adjustable delay time and optional trimming the gate at the end. To be used elsewhere in the synth as well. So I came up with this solution. The hardware is still simple and the functionality lies in the software. So far I have only realized the function which I need for my Shakuhachi to Synth project. But you can easily improve about this with changing the software.
The documentation and the Gerber files for download can be found in my website.
This is an old project dated back to December 2017. It was intended to learn some basics about the hard- and software of the ATMEGA series from AVR. It is kept simple. Just three analog inputs, one interrupt input and PWM output with filter are used. It is up to you what software you want to run on it. Here I made a simple voltage controlled VCO with variable symmetry. Speed, waveform and symmetry are voltage controlled. So you can change the triangle from ramp up to triangle to ramp down. Or make one halve of the sine very small. See screenshots below. This software was mainly written to test the hardware. To my surprise it worked sufficiently well for a LFO. So I leave it as is for the moment. No fancy accumulation with fixed point arithmetic and increment interpolation. Of course there is a lot room for improving the software. I know.
The documentation and the Gerber files for download can be found in my website.
This is the software driven replacement for my all hardware pitch to voltage converter from my Shakuhachi to Synth project. The software driven approach has the advantage of easily adaption for different frequency ranges. In my case it is the range of the Shakuhachi. To change the range just adapt the software. It is completely temperature independent. The needed input is a pulse train derived from your original signal. You can use my Signal to Trigger converter to provide the pulse train. An offset voltage is added to the V/Oct output to fit the needs of your VCO (Synthesizer).
The documentation and the Gerber files for download can be found in my website.
The incoming pulse train is feed to the microprocessor. IC1 (301-F) prevents the microprocessor from negative inputs. Zener D2 prevents from overvoltage. The trigger starts an internal timer of the microprocessor in input capture interrupt mode. The ticks are counted and the count is then looked up in a table. The lookup table provides the values for the V/Oct conversion. The read value is the send to the DAC MCP4921 which is follwed by a low pass (IC1A, 301-B)). IC2A (301-F) adds the offset voltage and IC2B (301-F) corrects the phase.
NGF-E Project: 440CPS front view
Not much to say. A 440CPS module. Quite useful for tuning in a bigger system. OK, one more sentence. It is the replacement for the 440CPS module from the Elektor Formant in my Next Generation Formant project Project.
Specs and features
• On/Off Switch to keep the 440Hz out of the system when not needed
• Runs on +/-15V and +/-12V
• Power consumption below 25mA +rail / 5mA -rail
The documentation for download can be found in my website.
NGF-E Project: 440CPS schematic
Everything is done in software. Output is a 440Hz Square wave. That’s it.
NGF-E Project: 440CPS populated PCB
NGF-E Project: 440CPS back view
Clock Divider with prime numbers
This clock divider divides the incoming clock signal down to the prime numbers /11, /13, /17, …. /31. The output is a 5V positive pulse. The length of the incoming pulse is kept. The trigger is on the rising edge of the incoming signal. The reset input can be used for syncing with other clocks. All outputs are buffered and brought out parallel with LED signaling the pulse.
Specs and features
• Regular input clock/square wave +5V
• Input signal divided by prime numbers
• Output +5V pulse with the length of the input signal (pulse)
• Runs with +15V/-15V or +12V/-12V (with minor changes)
The documentation for download can be found in my website.
Clock Divider with prime numbers, schematic
Most work is done by the microprocessor. The micro takes care of the input and output timing. All outputs are independently buffered. The clock is made visible with LED.
Clock Divider with prime numbers, populated PCB
Clock Divider with prime numbers, rear view
Looping ADSR front view
This Module is build around the LOOPENV 1B Pic chip from Electric Druid.I have bought the pic chip and added some protection and level shifting circuitry around it. For details of that chip please refer to the original documentation from Electric Druid.
The documentation for download can be found in my website.
Looping ADSR: schematic
Nothing special here. Just some standard input protection for the pic chip and a filter for the PWM signal to generate the output voltage.
Looping ADSR: populated PCB
Looping ADSR: back view